enum flash_instruction
{
    INST_NONE = 0  ,     
    INST_WRITE1B   ,
    INST_READ      ,
    INST_READ_SREG1,
    INST_READID    ,
    INST_CE        ,
    INST_SE        ,
    INST_BE32      ,
    INST_BE64      
};
#define RX_BUF_ADDR_START         0x50004000 
#define RX_BUF_ADDR_END           0x50004FFF
    
#define TX_BUF_ADDR_START         0x50005000  
#define TX_BUF_ADDR_END           0x50005FFF
#define CTRL_REGS_ADDR_START      0x50006000
#define CTRL_REGS_ADDR_END        0x50006FFF
    
#define CLK_PRESCALE_2		      0x02 /**< PCLK/2 Prescaler */
#define CLK_PRESCALE_4		      0x04 /**< PCLK/4 Prescaler */

#define CLK_MODE_1		          0x01 /**< SPI CLK MODE 1 */
#define CLK_MODE_0		          0x00 /**< SPI CLK MODE 0 */

#define FLASH_START_WORK          0x01 /**< FLASH START WORK(配置完成后) */
    
#define CONFIG_CLK_SET		      0x01 /** config reg[0] clk set       --> SPICLK_DIV_REG */
#define CONFIG_CLK_RESET          0x02 /** config reg[1] clk reset     --> PCLK/4 */
#define CONFIG_CLK_MODE_SET       0x04 /** config reg[2] clk mod set   --> SPICLK_MODE_REG[0] */
#define CONFIG_CLK_MODE_RESET     0x08 /** config reg[3] clk mod reset --> 1 */

enum flash_reg_offset
{
    COMD_REG_OFFSET = 0   ,     
    ADDR_REG_OFFSET       ,
    DATA_LEN_REG_OFFSET   ,
    SPICLK_DIV_REG_OFFSET ,
    SPICLK_MODE_REG_OFFSET,
    DEVICE_ID_REG_OFFSET  ,
    STATUS_REG_OFFSET     ,
    START_REG_OFFSET      ,
    CONFIG_REG_OFFSET     
};

// /**
//  * This typedef contains configuration information for the device.
//  */
// typedef struct {
// 	u16 DeviceId;		/**< Unique ID  of device */
// 	u32 BaseAddress;	/**< Base address of the device */
// 	u32 InputClockHz;	/**< Input clock frequency */
// 	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
// } spiflash_Config;